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Multiplicity Shift Register Setup
For Shift Register (SR) 0,
1, and 2 set the 4 MHz and 50 MHz gate and
Pre-Delay. Select the histogram size for
each SR. The 4MHz Gate and Pre-Delay
must be at 0.250 micro-second intervals and
the 50 MHZ Gate and Pre-Delay ate 0.020
micro-second intervals. When a value is
entered it will be reset to the closest
correct value.
Totals counters may take their input from
the TTL inputs or from the Differential
inputs.
SR 2 inputs are OR'ed together from the
selection of Totals inputs.
The List Mode input may be from the TTL
input or the Differential input.
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